Circulating current minimization scheme for a read-only memory

ABSTRACT

A linear transformer read-only memory of the type having an array of magnetic cores linked in different combinations by a large number of drive lines. Each core is also linked by an individual sense winding. Whenever a particular drive line is pulsed, the resultant current produces an output across the sense windings of those cores which that drive line links. The drive lines are divided into groups with all drive lines of a given group being connected through a common junction point to a source of current. Circulating leakage currents in the drive lines are reduced by making the average physical separation between electrically interconnected drive lines greater than the average physical separation between electrically unconnected drive lines.

United States Patent Furst et al.

CIRCULATING CURRENT MIN lMl ZATION SCHEME FOR A READ-ONLY MEMORY Inventors: Jozef Furst, Mission Viejo, Calif.;

J. Kjell Hovik, Irvine, Calif.

Assignee: Datapac, Incorporated, Santa Ana,

Calif.

Filed: Aug. 10, 1970 Appl. No.: 62,520

US. C1..340/174 SP, 340/174 DC, 340/174 MA Int. Cl ..G1lc 17/00, G1 1c 5/04, G1 1c 11/06 Field of Search ...340/l74 GA, 174 DC, 174 8?,

340/174 MA, 174 LA References Cited UNITED STATES PATENTS 1 4/1966 Byron et a1 ..340/174 SP 3/1971 Jallen ..340/l74 LA 2/1970 Wennstrom ..340l174 SP [451 Dec. 5, 1972 Primary Examiner-Stanley M. Urynowicz, Jr. Attorney-Fowler, Knobbe & Martens [5 7 ABSTRACT A linear transformer read-only memory of the type having an array of magnetic cores linked in different combinations by a large number of drive lines. Each core is also linked by an individual sense winding. Whenever a particular drive line is pulsed, the resultantcurrent produces an output across the sense windings of those cores which that drive line links.

The drive lines are divided into groups with all drive lines of a given group being connected through a common junction point to a source of current. Circulating leakage currents in the drive lines are reduced by making the average physical separation between electrically interconnected drive lines greater than the average physical separation between electrically unconnected drive lines.

3 Claims, 8 Drawing Figures PAIENTEDum 5 I972 SHEET 2 [1F 6 A T TOE/V5 V51 PATENTED 5 I97? 3,705,420

SHEET '5 BF 6 INVENTORS JOZEF FUFS T 4 TTOE/VEVS'.

CIRCULATING CURRENT MINIMIZATION SCHEME FOR A READ-ONLY MEMORY The present invention relates to an improvement in read-only memories as distinguished from memories of the type into which information can be written as well.

In orderto appreciate the advantages and special problems-of read-only memories, it is helpful to consider briefly' the read-write type of magnetic core memory. An example of this type of memory is described in U. S. Pat. No. 2,736,880 issued to J. W. Forrester. Typically it includes a stack of several magnetic core memory planes, all of which have magnetic cores arranged in corresponding rows and columns. Within each memory plane all of the cores in a given row are linked, i.e. threaded through, by an individual row drive line and similarly all cores in a given column are linked by an individual column drive line. Usually the memory is organized to store a multi-bit word of information in each group of cores which are corresponding located in the several memory planes so that one bit is stored in each core. The number of words which can be stored in the memory will equal the number of correspondingly located memory cores, that is, the number of cores in a single memory plane.

Assuming for example a magnetic core memory stack having four memory planes, each with 16 cores arranged in four rows and four columns, the memory will be capable of independently storing sixteen words, each word having four bits of information distributed between correspondingly located cores in the four planes.

A word is written into memory for storage by switching a selected plurality of cores at a given address, or location, into a particular one of two bistable magnetic states. This may be achieved by concurrently sending a current pulse in a particular direction through the row and column drive lines linking the selected cores. To read information stored at a particular address, a pulse of current is concurrently sent in the opposite direction through the row and column drive lines linking the coresat that address. Those cores which had not beenswitched during the writing operation will be unaffected, while the remaining cores at the interrogated address will have their magnetic states reversed during the reading operation. This reversal of magnetic state is detected by sense windings of which there is a respective one in each of the four memory planes.

It is worthy of note that in a typical magnetic core read-write memory, each core is linked by only two drive lines, and stores only one bit of information, that information is stored by reversing the magnetic state of a core, and that a large number of different words can be stored successively in every word location in the memory.

A read-only memory is one in which information is permanently stored and from which information canbe repetitively read. The present invention is concerned with improvements in linear transformer read-only memories which resembleread-write magnetic core memories in that they too utilize magnetic cores. There are, however, fundamental differences. First, information is stored in-a read-only memory, not by switching the cores between their two stable magnetic states, but by simple transformer'action in which current through a drive line coupling a given core is detected by a sense line coupling only that core. Secondly, instead of a matrix of magnetic cores threaded by row and column drive lines, the linear transformer read-only memory has an array of magnetic cores, selected ones of which are coupled by a large number of drive lines. In a typical linear transformer read-only memory there may be a series of 100 magnetic cores and a bundle of 512 drive lines. Each drive line will link anywhere from none to all of the 100 magnetic cores and the combination of cores linked by a given drive line will represent the binary information stored in the linear transformer read-only memory by virtue of that. particular drive line. Each drive line is connected to a current source through a separate switch or switches so that it may be driven to the exclusion of all other lines, thereby causing the data encoded by it into the cores of the memory to be read out. It is notable that each core stores as many bits of information as there are drive lines because each core serves to store a given bit location of a word associated with each one of the 512 drive lines linking the linear transformer read-only memory. This large increase in the use made of each core is a direct result of the fact that each core is linked not by a single drive line and a single column line, but by hundreds of drive lines. It is also significant that information is stored in aparticular core of the linear transformer read-only memory by the selective threading or bypassing of that core by the drive lines of the memory, rather than by switching of the core.

The much larger storage capability of a core in the linear transformer-read-only memory is achieved partly at the expense of flexibility, since. the information stored is physically encoded by the location of the drive lines and can be changed only by physically rearranging them. Additionally, the large number of very closely spaced drive lines results in a considerable capacitance between those lines. It has been found in the past that the undesired effects of the inter-drive line capacitances may be reduced by connecting several of the drive lines to one another at one of their ends. This interconnection between drive lines has the effect of producing a low resistance shunt which short circuits the capacitances between connected lines atleast in the vicinity of the connection. However, it has been found that, while the coupling of current from one line to the next is reduced by'connecting their ends, another problem is aggravated. In particular, where a given line is driven and it links a particular core which is also linked by a second line to which a third line is both physically close and electrically connected but which third line does not link the core, the second and third lines form a circuitthrough which a current will circulate due to the magnetic coupling between the first and second lines through. the core. Moreover, the current through the second drive line will flow in an opposite direction to the current in the first line, thereby tending to diminish the magnitude of the voltage induced in the sense winding of the core by the drive current in the first winding. In effect, the second and third drive lines function similarly to a shorted turn on a transformer.

In addition to diminishing the output across the sense winding of a core linked by the driven line, the circulating current also has the undesirable effect of inducing false signals in the sense windings of other cores which are linked by the second and third, non-driven, drive lines, the result of the combined effects of inducing false signals in some sense windings while reducing the magnitude of valid signals across other sense windings places significantly greater demands on the ability of the memory's sensing circuitry to distinguish between valid and spurious output signals.

The above problem is recognized and alleviated according to the invention by so distributing the drive lines that those drive lines whose ends are electrically connected are physically separated by a significantly larger amount than are electrically unconnected ones of the drive lines. This is shown herein to be achieved by dividing the drive lines into physically proximate groups and connecting to each of a series of points a single drive line from each of the groups. The invention also contemplates a particularly effective method for achieving the increased average physical separation between electrically connected drive lines. According to this method the drive lines are installed one after another so that successively installed ones of the drive lines are particularly close, preferably adjacent, to one another. These drive lines are then divided, in the order in which they have been installed, into groups of equal number. One line from each group is electrically connected to a first common point, a second drive line from each group is connected to a second common point and so on until every drive line in each group is connected to a different point in common with a corresponding drive line in every other group. By virtue of the face that unconnected drive lines are purposely made to be close to one another, it follows that connected drive lines are significantly farther separated from one another and hence have less distributed capacitance between them than those drive lines between which an electrical connection exists, thus making it more difficult for circulating currents to flow. Viewed differently, between most pairs of electrically connected drive lines there are interposed, as separating spacers, one or more drive lines which are connected to neither one of the pair.

The invention may be more clearly understood with reference to the following description of a preferred embodiment thereof taken in conjunction with the accompanying drawings in which:

FIG. 1 is a perspective schematic diagram illustrating the general arrangement of a linear transformer readonly memory threaded by a number of drive lines;

FIG. 2 is a simplified schematic diagram illustrating the paths for leakage currents through closely spaced drive lines connected to a common resistor;

FIG. 3 is a simplified schematic diagram illustrating the paths for leakage currents through the same drive lines when connected to separate load resistors;

FIG. 4 is a simplified perspective view of a series of cores of the type shown in FIG. 1 and the distribution, in general, of drive lines along those cores in accordance with the invention;

FIG. 5 is a cross-section through FIG. 4 along lines 55 to illustrate the distribution of drive lines in greater detail;

FIG. 6 is a partial schematic diagram illustrating the electrical connection of the drive lines shown in FIG. 5 at one oftheir ends;

FIG. 7 is a simplified perspective view ofa portion of a read-only memory wherein the drive lines are arranged in accordance with the present invention; and

FIG. 8 is a schematic diagram of a circuit suitable for controlling the flow of read current through the drive lines shown in FIG. 7.

The basic concept of the linear transformer readonly memory is illustrated in FIG. 1. It is comprised principally of a plurality of magnetic cores 11 each of which consists of a U-shaped core piece 13 and an shaped core piece 15. Threaded through the core 11 are a number of drive lines usually hundreds, of which only six, the drive lines l7a-17f, are illustrated. When the memory is in use, the I core pieces 15 are pressed tightly against the legs of their corresponding U core pieces 13 to form a continuous magnetic flux path so as to establish for each core 11 magnetic coupling between drive lines linking the cores and sense windings 16 which are wound around the 1 core pieces 15. Each drive line 17 is used to store a desired combination of bits in the memory. The usual arrangement is to make each core 11 represent a bit having a different binary significance. Thus, in the illustrated memory the leftmost core 11 might represent the lowest order bit, the one to its right the next higher order bit, and so on. Assume, for example, that a particular bit combination is to be encoded into the memory by means ofa given word line, such as the line 17a and that the combination is to have a binary 1 only at its second lowest order bit, and a binary 0 at all of the other bit positions. The winding will then be threaded as shown in FIG. 1, namely it will bypass all of the cores 11 except the second one from the left. Whenever a current pulse is driven through the line 17a, will be magnetically linked to the sense winding 16 of that core and to none other, and the proper bit combination will therefore appear on the sense winding 16 collectively. The line ll7b, on the other hand, encodes, or stores, a binary l at the first, second, third, fourth, seventh, l0th I 1th and 12th positions and binary Os at the fifth, sixth, eighth and ninth positions respectively.

A heretofore preferred way to drive a read current through a selected one of the drive lines 17 is illustrated in FIG. 2. Basically, each of the drive lines 17 is connected to a common point I which in turn is connected through a current limiting resistor 18 to the positive terminal 21 of a power supply having a pair of outputs for driving current through a load connected between them. The opposite ends of the respective drive lines 17 are individually connected through a series of switches 19 to the negative terminals 23 of the current source. It will be understood, of course, that there will be many groups of drive lines, such as those shown in FIG. 2. Each of these groups will be connected at one of their ends through a separate junction point I and through a separate current limiting resistor 18 to the positive current supply terminal 21 and respective ones of them will be connected through individual control switches 19 to the negative supply terminal 23. For purposes of the following discussion the drive lines 17a, 17b, 17d, l7e, and 17fof FIG. 1 have been selected with particular reference to the second core 11b illustrated in FIG. 1. The remaining cores and the drive line shown in FIG. 1 are omitted.

The driving arrangement illustrated in FIG. 2 is used with linear transformer read-only memories because the connecting together of all of the drive lines 17 at the point J tends to reduce the capacitance between them. However, this interconnection aggravates another problem, namely the flow of circulating currents through physically closely spaced pairs of electrically connected drive lines. Let it be assumed, for example, that a READ current la is driven through the drive line 17a by closing its associated control switch 19a. Since only a single drive line receives a READ current at at time, all of the switches 19 associated with the remaining drive lines are shown in the open position. The core 11b is shown to be linked by the drive lines 17b and 17f, and to be bypassed by the drive lines 17d and 17e. Let it be assumed that all of the non-driven drive lines 17b, 17d, l7e and l7fare physically close to oneanother. The result is that the linking drive line 17b is capacitively coupled to the non-linking drive line 17d through stray capacitances 27bd1 and 27bd2, the first of which is. between those portions of the drive lines between the core 11b and the junction point J, and the second of which is between the core and the switches 19. The drive line 17b is also capacitively coupled to the other non-linking drive line l7e through stray capacitances 27be1 and 27be2. Similarly, stray capacitances also appear between the linking drive line 17f and the non-linking drive lines 17d and 17e, as shown in FIG. 2. Since the drive line 17a receiving the READ current is magnetically coupled through the core 11b to the non-driven, linking drive lines 17b and 17]", the READ current will induce secondary currents lb and If in them respectively. A return path for the secondary induced current Ib is established through the non-linkingdrive lines 17d and 17e by virtue of the short-circuit between their ends connected to the junction point I and the stray capacitances 27bd2 and 27be2 between respective ones of the non-linking drive lines 17d and l7e and the linking drive line 17b.

The secondary current lb in the linking drive line 17b will flow in a direction opposite to the primary, or READ, current Ia, thus having the effect of diminishing the signal coupled to the sense winding of the core l1b..

A similar effect will also take place by virtue of a loop established by the drive lines 17f, 17d and 17e. In particular, a secondary current IF induced in the linking drive line 17f will find return paths through the nonlinking drive lines 17d and 17e by virtue of the connection at point J and the stray capacitances 17fd2 and l7fe2 coupling the linking line 17f to the non-linking lines 17d and l7e. The circulating secondary current If induced in the linking drive line 17f will reinforce the undesired effect of the circulating secondary current lb in the linking drive line 17b, tending further to reduce the signal induced in the sense winding of the core 11b. It will be noted that a portion of the circulating current will flow from the linking drive line 17b to the nonlinking drive lines 17and l7e through stray capacitances 27bdl and 27be1 coupling those lines and that similarly a connection between the linking drive line 17f and the non-linking drive lines 17d and 17e will also be established through the stray capacitances 27fdl and 27fe1 between those lines. However, because of the lower impedance maintained through the junction point J, the significance of the stray capacitance between those portions of the drive lines which extend between the core. 11b and the junction point J is reduced. The point to be observed with reference to FIG. 2 is that the non-linking drive lines 17d and l7e form a loop together with the linking drive lines 17b which is unbroken but for the stray capacitances 27be2 and 27bd2. Moreover, those same non-linking drive lines also form such a loop in combination with the other linking drive line 17f which again is unbroken but for the capacitances 27fe2 and 27fd2 which complete them.

FIG. 3 illustrates the principle underlying the present invention, namely that the problem of circulating current caused by inter-drive line capacitances is less acute if lines which are close to one another are not directly inter-connected. FIG. 3 shows the same components which are illustrated in FIG. 2 but each drive line 17 is shown to be connected to a different junction point J, each of which is connected to the +V terminal 21 through a different load resistor 18. It will be understood that, as was the case with FIG. 2, a set of drive lines will typically be connected to each of the junction points J. However, to illustrate the principle involved, each junction point J is shown to have only one drive line connected to it. If, then, the drive lines 17a, 17b, 17f, 17d, and 17e are physically disposed exactly .as they were in FIG. 2 so that the same capacitances exist between them, and if a READ current is driven through the drive line 17a so that secondary currents lb and If are induced in thedrive lines 17b and 17f respectively, it will be immediately apparent that the return paths for these induced currents will have a higher impedance with the arrangement of FIG. 3 then they did with the circuit of FIG. 2. The reason is that the short-circuit between the linking drive line 17b and the non-linking drive line 17d at point J in FIG. 2 has been replaced by the combined impedances of their respective load resistors 18B and 18D. Similarly, the short-circuit between the same linking drive line 17b and the other non-linking drive. line l7e is replaced by the impedances of their load resistors 18B and 18E. As a result, the returnvpaths for circulating currents between the linking and non-linking drive lines are completed through the stray capacitances 27be1, 27bdl, and 27fe1 and 27fd1 and through the resistors 18, whose combined admittance is considerably less than that of a direct connection at J. The secondary currentlf induced in the linking drive line 17f will line a similarly increased impedance between the line 17f and the drive lines 17d and l7e.

The principle illustrated by FlGs. 2 and 3, then, is clear. If two drive lines are closely spaced, the circulating current through them will be reduced if they are connected to separate current limiting resistors. Those drive lines which are electrically connected at one of their ends should be kept as far apart from one another as possible. The way in which this is achieved in accordance with the present invention is illustrated in FIGS. 4-6.

Generally, the drive lines are distributed in a predetermined pattern through and around the cores so that successive ones of them are purposely stacked adjacent to one another while at the same time each drive line serves to separate certain other drive lines. Careful track is kept of those drive lines which are closest to one another and individual members of these closely disposed drive lines are each connected to a different load resistor. In this way the likelihood of electrically interconnected drive lines being adjacent one another is minimized since, in most instances, several drive lines will be interposed between any pair of drive lines which are connected to a common point.

Referring more specifically to FIG. 4, the general distribution of a plurality of drive lines 17 with reference to a plurality of U core pieces 13 as shown. It is assumed that there are a total of 128 drive lines and that for purposes of wiring they are arbitrarily divided into 16 groups containing eight drive lines each. As shown generally in FIG. 4, the first group of eight drive lines is disposed generally to the bottom left of the series of U core pieces 13, while the second group of drive lines is located along the right bottom portions of the core pieces. To maintain a balance between the number of drive lines on opposite sides of the core pieces, the groups are alternated so that the third and each subsequent odd group is located above group 1 and each subsequent even numbered group is located above group 2. It will be noted that FIG. 4 is schematic in nature since obviously some of the drive lines will go through and not around the core pieces 13. Consequently, FIG. 4 shows only the general disposition of the groups of drive lines 17 relative to the U core pieces 13. Actually, individual drive lines will thread away from the bundles which extend generally outside of the cores and will enter, extend through, and exit back into the bundles through various ones of the core pieces 13. This is better shown in FIGS. 1 and 5.

One method of distributing the drive lines as shown in FIGs 4 and 5 is to successively thread each individual drive line, one after another, on the core pieces 13 and to place each successive drive line next to the previous one so threaded. In practice, it has been found that, rather than obtaining a single layer of drive lines extending upwardly from the bottom to the top of the core pieces 13, the drive lines become distributed in about three layers so that on each side of the column of cores the first three drive lines are at the bottom, the next three drive lines are above the first three and so The drive lines, of which 128 are indicated in FIG. 5, are then arbitrarily divided equally into a number of groups, each group having a number of drive lines corresponding to the number of common points J to which the various drive lines are to be connected. This will in turn dictate the total numbers of groups into which the drive lines are divided. For sake of example, as shown in FIG. 6, eight such common points, shown as the junctions JO-J7 have been selected, thereby causing the 128 drive lines to be divided into 16 groups of eight drive lines each.

In accordance with the invention, drive lines within each group are on the average more closely spaced to one another than drive lines belonging to separate groups. This is most conveniently achieved by selecting the bottom left eight drive lines, DLO-DL7 to constitute the first group, the bottom right eight drive lines DL8-DL15 to constitute the second group and so on all the way to the top right eight drive lines DL120-DL127 constituting the 16th group of drive lines. Then, as best shown in FIG. 6 one drive line from each group is connected to the first junction point JO, the second drive line from each group is connected to the second junction point J1, and so on until each junction point Jl-J7 has connected to it a set of drive lines which includes one drive line from each group. Since only one drive line from each group is connected to any given one of the junction points J, it follows that every drive line in a given group is connected to a different junction point, and most of those drive lines which are electrically con nected to a common junction point J are separated by one or more drive lines which are connected to neither of them. What is thus achieved is that the average capacitance between drive lines that are connected to a particular common point is significantly less than the average capacitance between drive lines that are connected to different ones of the several common points.

A close study of FIG. 5 will reveal that it is still possible for drive lines which are members of adjacent groups to be next to one another and, since they are in different groups, also to be connected to the same junction point J. However, the statistical probability of this occuring is much less than the statistical probability of electrically connected drive lines being next to one another when they are randomly connected regardless of their physical location relative to one another. To put it differently, by dividing the drive lines into groups and connecting each drive line of a group to a different point electrically, the number of drive lines which are both physically adjacent and electrically connected is greatly reduced.

FIG. 7 shows a suitable layout for a linear transformer read-only memory utilizing the drive line arrangement disclosed herein. Principally, it includes a plurality of U-shaped core pieces 13 arranged in two adjacent columns upon a printed circuit board 25, with their legs projecting upwardly through a pair of opening in the board and their central portions being held against its bottom. The I-shaped core pieces 15 described previously with reference to FIG. 1, are similarly mounted on a mating printed circuit (not shown) which when assembled together with the printed circuit board 25 causes each I-shaped core piece 15 to be pressed tightly against its corresponding U-shaped core piece 13 to form a complete magnetic core. Most of the electronic equipment used with the memory, such as drive line control switches and sense amplifiers are also mounted on the mating printed circuit board.

Extending along one side of the core pieces 13 is an array of terminals 28 which are anchored upon the printed circuit board 25 in an array having eight rows and 16 columns so that there is one terminal for each of 128 drive lines. A guide post 29 is mounted next to each column of eight terminals 28 and all drive lines from each column of terminals 28 are initially wrapped around the particular post 29 next to that column.

Extending along the opposite side of the core pieces 13 are a series of eight terminals 31, one for each of the eight sets of sixteen drive lines which are to be connected to a common point as explained with reference to FIG. 6. The terminals 31 correspond electrically to the junction points JO-J7 of FIG. 6 and will be referenced as such in the following description.

Drive lines are installed by threading them singly in succession from respective ones of the terminals 28 past or through the cores 13 and connecting them to successive ones of the terminals JO-J7. Thus, the first drive line DLO is threaded from thetop right terminal 28 0, wrapped around the post 29-1, and is brought along the next to the bottom portions of the other posts 29-2 through 2916 and is then threaded past some and through other ones of the U core pieces 13 as dictated'by the particular combination of bits which is to be encoded by that particular drive line. In order to simplify the drawing, all of the drive lines in FIG. 7 are shown to bypass all of the cores, as was done in FIG. 5.

After leaving the last of the core pieces 13 the drive line DLO is electrically connected to the first terminal 10. It will be noted that, throughout its passage next to the guide posts 29 and next to the cores 13, the drive line DLO will be held quite close to the board 25. The next drive line DLl is similarly brought past the guide posts 29 and the core pieces 13 immediately adjacent to the first drive line DLO and is electrically connected to the second junction point J1. In a similar manner, successive ones of the drive lines DL2 through'DL7 are brought along next to the drive lines DLO and DLl, each drive line being next to the previous one but preferably slightly above it. Also, each successive one of the drive lines DL2 through DL7 is electrically connected to a successive one of the terminals J2-J7 so that each of these physically proximate drive lines is electrically connected to a different point. The same process is then repeated with the drive lines DL8 through DL 15, leading each of them in succession from respective ones of the terminals 28 in the second column of such terminals from the right, again connecting successive ones of them to respective ones of the terminals JO-J7. This process continues until all 128 drive lines DLO through DL127 have been installed, forming a braid of closely spaced wires.

Throughout the threading process, as effort is made to lead each drive line along the top of the previously threaded drive line both in the vicinity of the guide posts 29 and next to the core pieces 13 so that, generally the physically location of the drive lines progresses upward, that is, in a direction which is away from the board 25, with each successive such drive line. In practice, it has been found that the drive lines will become distributed in several adjacent layers, with wires still progressing generally upwardly in the order in which they are installed, but not in a single column. This is best seen in FIG. 5.

A suitable circuit configuration for the assembly of FIG. 7 is shown in FIG. 8. The drive lines DLO through DL127 are electrically separated into eight sets, drive lines within each set being electrically connected to a respective one of the junction points .lO-J8. Each set of drive lines is controlled by a respective row of transistor switches 19 in a sixteen column switch matrix of which only the first three and last two columns are shown. The physical distribution of the drive lines within each set is as explained previously. That is, within each set every drive line is connected to a differentjunction point J.

Each switch 19 is the matrix has a first and a second input which must be concurrently enabled in order to close the switch. A common row control line connects the first inputs of all switches in a given row and a common column control line connects the second inputs of all switches in a given column. Thus, any switch may be selected by enabling the row and column control line to which it is connected.

To select a particular drive line for reading, a group of seven binary signals A to A6 are applied to a pair of decoders 33 and 35. The X decoder 33 converts the first three bits of the binary signal group into an output on one of its eight output lines and the Y decoder 35 similarly converts the last four bits into an output signal on one of its 16 output lines. Each output of the X decoder33 serves to select a particular row of switches 19 and each output line of the Y decoder 35 performs that function through an intermediate current switching block 36 for each column of transistor switches.

As was just noted, each transistor switch 19 in the matrix has two inputs, the emitter and the base, both of which must be enabled in order to close the switch. A series of column control lines 37 connect the first inputs (the emitters) of all switches in the respective columns and are connected at one of their ends through individual bias resistors 39 to the +V potential at terminal 21. At their opposite ends each of the column bus lines 37 is connected through the collectoremitter circuit of a respective one of a series of transistor control switches 41 in the current switching block 36 to the -V potential level maintained at the terminal 23. The transistors 41 are normally biased into non-conduction by connecting their bases through biasing resistors 43 to the +V potential level. To turn on a selected one of the transistors 19, a signal is applied to its base through an inverter'45 driven by a corresponding output of the decoder 35. The signals produced by the Y decoder 35 on its outputs are such that when any one of them is inverted, it is operative to turn on a selected one of the transistors 41, causing the emitters of all of its associated column transistor switches 19 to be pulled down to the V potential level which is one condition for the transistor switches in that column to be turned on.

Another condition for turning on any particular transistor switch 19 in the matrix is that its base be shifted from the level at which it is normally held. In particular, a series of row control lines 47 connect the bases of all of the transistor switches 19 in a given row through row bias resistor 49 to the +V potential level. Thus, normally the bases of all transistor switches 19 are maintained at a potential which is the same as that at which their emitters are held so that they are all biased into non-conduction. To enable the transistor switches 19 in any given row of the matrix, each of the row control lines 47 is also connected through a respective inverter 51 to a different one of the eight outputs of the X decoder 33. When a signal is caused to appear on the output of the decoder corresponding to the selected row of transistor switches 19, it is inverted by the inverter 51 to a level which is operative to turn on the transistor 19 to the base of which it is applied, provided that the transistor is also in a column selected by the signals being applied to the Y decoder 35.

It is desirable that an auxiliary impedance 55 be connected between the junction point .I of each set of drive lines 17 and the V potential terminal through the collector-emitter circuit of an impedance control transistor switch 57 corresponding to the similarly numbered components in FIGS. 3 and 4. The base of the transistor 57 is connected through a base biasing resistor 59 to the +V potential level so that, in the absence of a signal at its base, the transistor is always biased to conduct. The base of each transistor 57 is also connected to a respective one of the outputs of the X decoder 33. Although not shown, this connection is preferably through two inverters connected in series with one another so that no logical inversion occurs but there is a power amplification between the output of the decoder 33 and the base of each impedance control transistor 57. In any event, a signal on any output of the decoder 33 is operative to turn off the transistor 57 to the base of which it is connected.

In the absence of a signal on an output of the decoder 33 associated with a given row of transistor switches 19, all of the transistor switches in that row are disabled and there is no drive current through any of the set of drive lines 17 controlled by them. So long as this condition continues, the corresponding impedance control switch 57 is biased to conduct, causing a compensating current to be drawn by its associated impedance 55 from the junction point J and through the current limiting resistor 18. As soon as a signal appears on the same decoder output, and assuming that a corresponding signal also appears on one of the outputs of the Y decoder 35, one of the control switches 19 in that row will close and their associated impedance control switch 57 will open. Thus, collectively, the several auxiliary impedances 55 and their associated impedance control switches 57 are operative to maintain a compensating current through each current limiting resistor 18 when, and only when, no drive current is drawn through it. In this way undesirable voltage fluctuations across the resistors 18 due to switching of current between drive lines are greatly reduced. This disclosed feature is not claimed herein in that it is the sole invention of Jozef Furst. instead it is disclosed and claimed in a co-pending patent application entitled DRIVE AR- RANGEMENT FOR READ-ONLY MEMORY, Ser. No. 62,519, filed Aug. 10, 1970, now US. Pat. No. 3,644,909 by Jozef Furst. and assigned to the assignee ofthc present invention.

Each particular auxiliary impedance 55 may be selected to have a different impedance value, depending upon the average impedance value of the set of drive lines to which it is connected. Alternatively, if a less accurate approximation of the drive line currents is sufficient, all of the auxiliary impedances 55 may be made to have the same impedance value, this being selected as the average impedance of all of the drive lines 17 of the memory.

What is claimed is:

1. ln a read-only memory the combination comprising:

a. a plurality of magnetic cores;

b. a braid comprised of a plurality of groups of drive lines linking said cores, drive lines within each group being on the average more closely spaced to one another than drive lines belonging to separate groups; and

c. a plurality of separate current paths, each connected between a current source and at least one drive line from each of said groups for feeding current thereto.

2. In a read-only memory the combination comprising:

a. a plurality of magnetic cores; b. a braid comprised of a plurality of sets of drive lines linking selected ones of said magnetic cores, all lines of each respective set being connected to a respective common point at one of their ends, said drive lines being so distributed physically within said braid that the spacing between drive lines connected to any particular common point is greater than the spacing between drive lines connected to different ones of said common points;

c. means having a pair of outputs for driving current through a load connected across said outputs;

d. separate current paths connected between respective ones of said common points and one of said outputs;

e. a plurality of switches, each connected between the opposite end of a respective one of said drive lines and the other of said pair of outputs; and

f. means for selectively closing a desired one of said plurality of switches.

3. In a linear transformer read-only memory the combination comprising:

a. an array of magnetic cores, each comprised of a U- shaped core piece capped by an l-shaped core piece, one of said core pieces having a sense winding wound thereon;

b. a plurality of groups of drive lines running along and principally outside both legs of said U-shaped core pieces, drive lines within each group being proximate along their length and passing inside said legs to magnetically couple selected ones of said magnetic cores;

c. means having a pair of outputs for driving current through a load connected across said outputs;

d. means for connecting to each of a series of common points one end ofa single drive line from each of said groups;

e. A separate current path having a preselected impedance connected between each said common point and one of said outputs;

f. a plurality of switches, each connected between the opposite end of a respective one of said drive lines and the other of said pair of outputs; and

g. means for selectively closing a desired one of said plurality of switches so as to generate an output on the sense windings of those magnetic cores linked by the drive line to which said switch is connected. 

1. In a read-only memory the combination comprising: a. a plurality of magnetic cores; b. a braid comprised of a plurality of groups of drive lines linking said cores, drive lines within each group being on the average more closely spaced to one another than drive lines belonging to separate groups; and c. a plurality of separate current paths, each connected between a current source and at least one drive line from each of said groups for feeding current thereto.
 2. In a read-only memory the combination comprising: a. a plurality of magnetic cores; b. a braid coMprised of a plurality of sets of drive lines linking selected ones of said magnetic cores, all lines of each respective set being connected to a respective common point at one of their ends, said drive lines being so distributed physically within said braid that the spacing between drive lines connected to any particular common point is greater than the spacing between drive lines connected to different ones of said common points; c. means having a pair of outputs for driving current through a load connected across said outputs; d. separate current paths connected between respective ones of said common points and one of said outputs; e. a plurality of switches, each connected between the opposite end of a respective one of said drive lines and the other of said pair of outputs; and f. means for selectively closing a desired one of said plurality of switches.
 3. In a linear transformer read-only memory the combination comprising: a. an array of magnetic cores, each comprised of a U-shaped core piece capped by an I-shaped core piece, one of said core pieces having a sense winding wound thereon; b. a plurality of groups of drive lines running along and principally outside both legs of said U-shaped core pieces, drive lines within each group being proximate along their length and passing inside said legs to magnetically couple selected ones of said magnetic cores; c. means having a pair of outputs for driving current through a load connected across said outputs; d. means for connecting to each of a series of common points one end of a single drive line from each of said groups; e. A separate current path having a preselected impedance connected between each said common point and one of said outputs; f. a plurality of switches, each connected between the opposite end of a respective one of said drive lines and the other of said pair of outputs; and g. means for selectively closing a desired one of said plurality of switches so as to generate an output on the sense windings of those magnetic cores linked by the drive line to which said switch is connected. 